Summary
# Introduction to hardware description languages
Hardware description languages (HDLs) are fundamental tools in digital design, enabling the specification, simulation, and synthesis of electronic circuits [4](#page=4).
### 1.1 The role of hardware description languages in digital design
A hardware description language (HDL) specifies only the logic function of a circuit. Computer-aided design (CAD) tools then use this specification to produce or synthesize the optimized gates that implement the desired function. The majority of commercial designs are built using HDLs [4](#page=4).
> **Tip:** When using an HDL, it's crucial to think about the actual hardware the code should produce and then write the HDL idiom that implies that hardware. Avoid treating HDLs like general-purpose software programming languages without considering the underlying hardware implications [6](#page=6).
### 1.2 Leading hardware description languages
Two prominent HDLs are SystemVerilog and VHDL [4](#page=4).
* **SystemVerilog:**
* Originated from Verilog, developed in 1984 by Gateway Design Automation [4](#page=4).
* Became an IEEE standard in 1995 [4](#page=4).
* Received extensions in 2005, leading to the IEEE STD 1800-2009 standard [4](#page=4).
* **VHDL:**
* Developed in 1981 by the Department of Defense [4](#page=4).
* Became an IEEE standard in 1987 [4](#page=4).
* Updated in 2008 to IEEE STD 1076-2008 [4](#page=4).
### 1.3 The process of simulation and synthesis
HDLs are integral to two key stages in the digital design workflow: simulation and synthesis [5](#page=5).
* **Simulation:**
* Involves applying inputs to the circuit described by the HDL and checking the outputs for correctness [5](#page=5).
* Debugging designs through simulation can save millions of dollars by identifying and fixing errors before actual hardware is produced [5](#page=5).
* **Synthesis:**
* This process transforms the HDL code into a netlist, which is a description of the hardware composed of gates and their interconnections [5](#page=5).
### 1.4 SystemVerilog modules
SystemVerilog utilizes modules to encapsulate hardware components. There are two primary types of modules [7](#page=7):
* **Behavioral modules:** These describe *what* a module does in terms of its functionality [7](#page=7).
* **Structural modules:** These describe *how* a module is constructed from simpler, interconnected modules [7](#page=7).
#### 1.4.1 Module declaration in SystemVerilog
A SystemVerilog module is declared using the `module` and `endmodule` keywords, which must enclose the module's definition. The name of the module follows the `module` keyword [8](#page=8).
**Basic structure:**
```systemverilog
module module_name(port_list);
// module body
endmodule
```
**Example:**
```systemverilog
module example(input logic a, b, c,
output logic y);
// module body goes here
endmodule
```
In this declaration:
* `module example`: Marks the beginning of a module named `example` [8](#page=8).
* `input logic a, b, c`: Declares three input signals of type `logic` [8](#page=8).
* `output logic y`: Declares one output signal of type `logic` [8](#page=8).
* `endmodule`: Marks the end of the module definition [8](#page=8).
#### 1.4.2 Behavioral SystemVerilog example
Behavioral descriptions often use constructs like the `assign` statement for combinational logic. This statement continuously assigns a value to a signal based on an expression [9](#page=9).
**Example:** Implementing a specific logic function:
```systemverilog
module example(input logic a, b, c,
output logic y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule
```
In this example:
* `assign`: Indicates a continuous assignment [9](#page=9).
* `y =...`: The expression on the right side is continuously evaluated and assigned to the output `y` [9](#page=9).
* `~`: Bitwise NOT operator [9](#page=9).
* `&`: Bitwise AND operator [9](#page=9).
* `|`: Bitwise OR operator [9](#page=9).
This specific expression describes a circuit that produces an output `y` that is true under certain combinations of inputs `a`, `b`, and `c`. The synthesis tool will convert this behavioral description into the corresponding gate-level logic [11](#page=11) [9](#page=9).
### 1.5 HDL simulation
Simulation is a critical step where the behavior of the HDL code is tested by applying input stimuli and observing the output responses. This allows designers to verify the functional correctness of the design before proceeding to hardware implementation [10](#page=10) [5](#page=5).
### 1.6 HDL synthesis
Synthesis is the process where the HDL code is translated into a netlist of standard logic gates. This netlist represents the actual hardware implementation. Tools analyze the HDL description, such as the continuous assignment shown in the behavioral example, and determine the minimum set of logic gates (AND, OR, NOT, etc.) required to implement that functionality [11](#page=11).
### 1.7 SystemVerilog syntax fundamentals
SystemVerilog has specific syntax rules that must be followed for correct interpretation by design tools [12](#page=12).
* **Case sensitivity:** SystemVerilog is case-sensitive, meaning `reset` and `Reset` are treated as different signals [12](#page=12).
* **Naming conventions:** Names for signals, modules, etc., cannot start with a number. For example, `2mux` is an invalid name [12](#page=12).
* **Whitespace:** Whitespace (spaces, tabs, newlines) is generally ignored by the compiler, aiding in code readability [12](#page=12).
* **Comments:** Comments are used to explain the code and are ignored during synthesis and simulation.
* Single-line comments start with `//` [12](#page=12).
* Multiline comments are enclosed between `/*` and `*/` [12](#page=12).
---
# Combinational logic and operators in SystemVerilog
This section explores how to describe combinational logic in SystemVerilog, focusing on various operators, conditional assignments, internal variables, operator precedence, and numerical representation for bit manipulations.
### 2.1 Describing combinational logic
Combinational logic circuits are characterized by their outputs being solely dependent on their current inputs. SystemVerilog allows for the direct description of such logic using assignments.
#### 2.1.1 Bitwise operators
SystemVerilog supports standard bitwise operators for performing logical operations on individual bits or entire vectors. These operators include [15](#page=15):
* **AND (`&`):** Performs a logical AND operation bit by bit.
* **OR (`|`):** Performs a logical OR operation bit by bit.
* **XOR (`^`):** Performs a logical XOR operation bit by bit.
* **NAND (`~&`):** Performs a logical NAND operation bit by bit (NOT AND).
* **NOR (`~|`):** Performs a logical NOR operation bit by bit (NOT OR).
**Example:**
> **Example:** A module demonstrating different two-input logic gates operating on 4-bit buses.
> ```systemverilog
> module gates(input logic [3:0 a, b,
> output logic [3:0 y1, y2, y3, y4, y5);
> assign y1 = a & b; // AND
> assign y2 = a | b; // OR
> assign y3 = a ^ b; // XOR
> assign y4 = ~(a & b); // NAND
> assign y5 = ~(a | b); // NOR
> endmodule
> ```
> [15](#page=15).
#### 2.1.2 Reduction operators
Reduction operators operate on a vector and reduce it to a single bit. They are particularly useful for compact representation of logic that would otherwise require extensive explicit bitwise operations [16](#page=16).
* **Reduction AND (`&`):** Returns true if all bits in the vector are 1 [1](#page=1).
* **Reduction OR (`|`):** Returns true if any bit in the vector is 1 [1](#page=1).
* **Reduction XOR (`^`):** Returns true if an odd number of bits in the vector are 1 [1](#page=1).
* **Reduction NAND (`~&`):** The negation of the reduction AND.
* **Reduction NOR (`~|`):** The negation of the reduction OR.
* **Reduction XNOR (`~^`):** The negation of the reduction XOR.
**Example:**
> **Example:** A module that implements an 8-bit reduction AND operation.
> ```systemverilog
> module and8(input logic [7:0 a,
> output logic y);
> assign y = &a; // Equivalent to a & a &... & a [6](#page=6) [7](#page=7).
> endmodule
> ```
> [16](#page=16).
#### 2.1.3 Conditional assignment (ternary operator)
The conditional assignment operator, also known as the ternary operator (`?:`), provides a concise way to assign a value based on a condition. It evaluates three operands: a condition, a value if the condition is true, and a value if the condition is false [17](#page=17).
The syntax is: `assign
Glossary
| Term | Definition |
|------|------------|
| Hardware Description Language (HDL) | A specialized programming language used to describe the structure, design, and behavior of electronic circuits, primarily for digital systems. HDLs allow designers to model hardware at various levels of abstraction. |
| Simulation | The process of modeling the behavior of a hardware design over time using test inputs to verify its functional correctness before physical implementation. This helps in identifying and debugging errors early in the design cycle. |
| Synthesis | The automated process of converting a high-level HDL description into a lower-level netlist of primitive logic gates and their interconnections, which can then be used for manufacturing. |
| SystemVerilog | An extension of the Verilog HDL, providing advanced features for describing, simulating, and verifying complex digital hardware designs. It is a popular standard in the semiconductor industry. |
| VHDL | (VHSIC Hardware Description Language) A standardized HDL developed for describing electronic circuits, particularly for use by the U.S. Department of Defense. It is known for its strong typing and verbose syntax. |
| Module | A fundamental building block in HDLs like SystemVerilog, representing a distinct hardware component with inputs and outputs. Modules can be behavioral, describing functionality, or structural, detailing internal construction. |
| Behavioral Description | A style of HDL modeling that focuses on the functional behavior of a circuit without specifying its precise gate-level implementation. It describes what a module does rather than how it is built. |
| Structural Description | A style of HDL modeling that describes a hardware component by explicitly instantiating and connecting simpler sub-modules or primitive gates, detailing its physical structure. |
| Combinational Logic | A type of digital logic where the output is solely determined by the current combination of its inputs, with no memory elements. Its output changes instantaneously with input changes. |
| Sequential Logic | A type of digital logic where the output depends not only on the current inputs but also on the past sequence of inputs, utilizing memory elements like flip-flops and latches. |
| Flip-Flop | A sequential logic element that stores one bit of information and changes its state only on the edge of a clock signal. It is a fundamental building block for memory and state machines. |
| Latch | A sequential logic element that stores one bit of information and holds its state as long as a control signal is active. Unlike flip-flops, latches are level-sensitive. |
| always_ff | A SystemVerilog construct used to describe sequential logic that infers flip-flops. It is sensitive to clock edges and is intended for describing clocked sequential elements. |
| always_comb | A SystemVerilog construct used to describe combinational logic. It automatically infers the sensitivity list to ensure that the logic is purely combinational, reacting to any changes in its inputs. |
| always_latch | A SystemVerilog construct used to describe latches. It infers a sensitivity list based on the signals that control the latching behavior. |
| Blocking Assignment | An assignment operator (`=`) in HDLs that executes sequentially. Once a blocking assignment is executed, the value is immediately updated, affecting subsequent statements within the same block. |
| Nonblocking Assignment | An assignment operator (`<=`) in HDLs that schedules an update to occur at the end of the current simulation time step. This prevents race conditions in sequential logic and allows for more predictable behavior. |
| Finite State Machine (FSM) | A computational model consisting of a finite number of states, transitions between those states, and actions performed. FSMs are widely used in digital design to control sequential behavior. |
| Moore FSM | A type of Finite State Machine where the output depends only on the current state. The output logic block determines the output based solely on the state register's current value. |
| Mealy FSM | A type of Finite State Machine where the output depends on both the current state and the current inputs. The output logic block considers both the state and input signals. |
| Parameterized Module | A module in HDL that includes parameters, allowing its behavior or structure to be customized during instantiation. This enables design reuse and flexibility for different word sizes or configurations. |
| Testbench | A separate HDL module designed to test and verify the functionality of another module, known as the "device under test" (DUT). Testbenches provide stimulus and check the DUTs responses. |
| Device Under Test (DUT) | The specific hardware module or circuit that is being tested by a testbench. Its inputs are driven by the testbench, and its outputs are monitored and verified. |
| Netlist | A description of a digital circuit in terms of its constituent logic gates and their interconnections. It is the output of the synthesis process and the input for physical design tools. |
| Sensitivity List | A list of signals in an `always` block that triggers the execution of the block's statements when any of the listed signals change. |
| Ternary Operator | A conditional operator (`?:`) in SystemVerilog that evaluates a condition and returns one of two values based on whether the condition is true or false. It takes three operands: condition, value if true, and value if false. |
| Reduction Operator | An operator in SystemVerilog that reduces a multi-bit operand to a single bit by applying a binary operation (like AND, OR, XOR) across all bits of the operand. |
| Bitwise Operator | Operators that perform logical operations on corresponding bits of two operands. Examples include AND (`&`), OR (`|`), and XOR (`^`). |
| Floating Output | An output state (`z`) in digital logic indicating that the output is neither a definite high (1) nor a low (0), often used in tri-state buffers to disconnect a driver. |
| Testvector | A set of input values and their corresponding expected output values used to verify the behavior of a hardware design. Testvectors are often stored in files for automated testing. |